The various circuit components on an integrated circuit generally need some form of isolation from one another. Commonly, p-n junction isolation is used to electrically isolate electronic components, such as transistors whether MOS or bipolar, on an integrated circuit by surrounding the respective components or groups of components with p-n junctions that are reverse biased during operation.
Some integrated circuits can experience unbalanced electrostatic charge which can cause an electrostatic discharge (ESD) if the electrical charge is balanced uncontrolled and fast. For integrated circuits (ICs), ESD reaching certain nodes may have significant impact on product quality and production yields. The discharge current of an ESD event may damage or destroy gate dielectrics (e.g., gate oxides), pn junctions and the metallization of ICs. For example, an ESD event may occur due to a charged body touching an IC or a charged IC touching a grounded surface.
NMOS transistors are commonly used for ESD protection. NMOS transistors offer ESD protection through activation of their parasitic NPN bipolar transistor. When a significant amount of current (e.g. ESD current) is forced to flow into an NPN transistor (e.g. collector-to-emitter), typically an IV-characteristic with a negative differential resistance area (“snapback” as it is generally called) is observed. Vt1 generally denotes the trigger voltage of snapback and Vt2 the trigger voltage of second breakdown (thermal destruction). Often Vt1 is larger than Vt2. In this case, Vt1 represents the maximum voltage that drops across the ESD protection element (or ESD cell) and causes overvoltage stress to circuits to be protected. Therefore it is desirable to reduce Vt1 as much as possible. This can be done by biasing the gate of the NMOS (e.g., Vgs) or by injecting current into the base of the parasitic NPN transistor (IB).
The holding voltage (Vh) represents the minimum voltage reached after snapback. If the Vh of an ESD transistor meant to protect circuitry coupled to a power supply pin is less than the maximum supply voltage, a voltage spike superimposed on the supply voltage may trigger the ESD transistor and the low Vh value will prevent the ESD transistor from being turned-off until it is thermally destroyed. To avoid this “latch-up” risk the Vh value should be greater than the maximum supply voltage used by the IC.
One first known ESD cell comprises a “substrate” triggered ESD NMOS transistor along with its parasitic NPN transistor and a simple transient trigger circuit such as a capacitor in series with a resistor coupled to the body of the NMOS (and thus to the base of the parasitic NPN transistor). The trigger circuit injects current into the base of the parasitic NPN transistor when the PAD voltage coupled to the drain of the NMOS transistor is suddenly increased due to an ESD event to the PAD with respect to the REF terminal which is coupled to the source of the NMOS transistor. A diode in parallel to the NMOS transistor is also provided for negative ESD current conduction. This first known ESD cell is not an isolated cell.
A second known ESD cell comprises a “substrate” triggered NMOS transistor that comprises the first known ESD cell with an added low-side diode in series between the source of the NMOS transistor and the REF terminal. This ESD cell has a Vh value that is generally sufficiently increased by the voltage drop that is developed upon an ESD event across the low-side diode. This second known ESD cell is junction isolated with all its components (NMOS transistor, low-side diode and the diode in parallel to the NMOS transistor) positioned in individual NBL/NWELL isolation regions separated and thus junction isolated from one another by p-type guard rings. The low-side diode reduces the (pumping) current injected into the base of the parasitic NPN transistor and hence raises the Vt1 of the ESD cell.